The present invention relates to a semiconductor integrated circuit including a test circuit that is usable as a scan chain, and more particularly, to a method for eliminating a hold error occurring in a scan chain.
With the scale of digital circuits increasing in recent years, automatic design using a design tool has improved design efficiency of digital circuits. Further, a test circuit for testing the operation of a designed logical circuit is also designed automatically. A scan chain, which is formed by series-connected data holding circuits such as flip-flops, is one technique for conducting the operational test using a test circuit. More specifically, a scan shift test is conducted by operating each of the data holding circuits as a shift register to determine whether the data holding circuit operates normally.
FIG. 1(a) is a schematic circuit diagram showing an example of a scan chain. A large number of scan flip-flops (hereafter referred to as “scan FFs”) 1a to 1f are arranged on a semiconductor chip. Each of the scan FFs 1a to 1f has a scan-in terminal SI and a scan-out terminal SO. During the operational test, the scan-out terminal SO of each scan FF is connected to the scan-in terminal SI of another scan FF so that the large number of scan FFs are connected in series.
During the operational test, each scan FF operates as a shift register and latches data provided to its scan-in terminal SI in accordance with a clock signal CK. The scan FF then outputs the latched data from its scan-out terminal SO. It is determined whether each of the scan FFs 1a to 1f is operating normally based on whether each of the scans FF 1a to 1f operates normally as a shift register.
During normal operation, the switching function of each of the scan FFs 1a to 1f disconnects the corresponding scan-in terminal SI and the scan-out terminals SO. After the disconnection, each of the scans FFs 1a to 1f is connected to another corresponding logical circuit so as to operate as a normal flip-flop.
To efficiently conduct the scan shift test using such a scan chain, the scan FFs need to be connected in a manner that a setup error and a hold error do not occur in each scan FF. For this purpose, designing of the scan chain involves the processing described below.
As shown in the flowchart in FIG. 3, the layout position and the wiring length of the scan FFs 1a to 1f are adjusted in a manner that a setup error does not occur in each of the scan FFs 1a to 1f that are connected to form a scan chain (step S1). Then, the hold timings of the scan FFs 1a to 1f are verified (step S2).
Next, the position of each hold error occurring in the scan FFs 1a to 1f is identified (detected), and a value representing a delay time required for eliminating each hold error is determined (step S3). A buffer for generating the necessary delay time is inserted at the position of each hold error (step S4). The timing verification is then performed again (step S5).
If all the hold errors have been eliminated, the setup timing and the hold timing of each scan FF are assumed to have converged on normal timings. The layout process of the scan chain ends (steps S6 and S7). If all the hold errors have not been eliminated, the processing in steps S4 and S5 is repeated.
FIG. 1(b) shows an example in which seven buffer circuits 2a to 2g for eliminating hold errors are inserted at the necessary positions between the scan FFs 1a to 1f. 
FIG. 2(a) is a schematic circuit diagram showing another prior art example of a scan chain. Each of the scan FFs 3a to 3d has an output terminal Q, which also functions as a scan-out terminal. The output terminal Q of the scan FF 3a is connected to the scan-in terminal SI of the scan FF 3b and to a logic cell 4a via two buffer circuits 2h and 2i. The output terminal Q of the scan FF 3c is connected to the scan-in terminal SI of the scan FF 3d and to a logic cell 4b via three inverter circuits 5a to 5c. 
FIG. 2(b) shows an example of scan chains in which buffer circuits 2j and 2k are inserted between the scan FFs 3a and 3b and buffer circuits 2m and 2n are inserted between the scan FFs 3c and 3d. These buffer circuits are inserted by the above processing to eliminate hold errors between the scan FFs 3a and 3b and between the scan FFs 3c and 3d. 
Japanese Laid-Open Patent Publication No. 11-203105 describes a technical concept for reconnecting the scan FFs to shorten the wiring length of the scan chain, and inserting buffer circuits to compensate for insufficient driving capability of the scan FFs.
Japanese Laid-Open Patent Publication No. 2003-256488 describes a technical concept for inserting buffer circuits to adjust the setup timings and the hold timings in the scan chain and reordering the scan chain.
Japanese Laid-Open Patent Publication No. 2003-167030 describes a technical concept for inserting a delay element in a scan data input circuit unit of a scan FF to eliminate hold errors. A transistor having a relatively high threshold is used as the delay element.
Japanese Laid-Open Patent Publication No. 2002-267723 describes a technical concept for alternately operating two scan flip-flops to eliminate hold errors.